View SM9103M_912128.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

SM9103M nippon precision circuits? nippon precision circuits inc. dvdram head ampli?r lsi overview the SM9103M is a photodiode photoelectric cur- rent-to-voltage conversion head ampli?r lsi for optical disk pickups in dvdram/dvdrom equip- ment. it sums the photodiode current data signals and then converts the signals to a differential signal for output. the output tracking servo and focusing servo signals are derived from built-in sum and difference circuits, and the gain for these servo signals can be adjusted using serial interface controls. each of the signals from the photodiodes, used to generate dpd (differential phase detection) tracking servo signal, is current-to-voltage converted and then also output. it operates from a single 5 v supply, and is available in 36-pin plastic ssop packages. features n ram/rom gain switching, low-noise rf signal generator (differential output) n rom tracking dpd signal output n variable-gain ram tracking push-pull signal out- put n address signal, high-speed push-pull signal output n variable-gain focus error signal output n tracking pd sum signal output n focus pd sum signal output n offset correction timing output (logic) n temperature monitor function n serial interface to control internal parameter set- tings n sleep-mode function n single 5 v supply n 36-pin plastic ssop typical applications n double-speed dvdrom equipment n double-speed dvdram equipment ordering information pinout 36-pin ssop (top view) device package SM9103M 36-pin ssop 1 mode 2 write 3 dgnd 4 dvcc 5 tempo 6 tempi 7 t1 8 t2 9 t3 10 t4 11 f1 12 f2 13 agnd 14 vref 15 fsubb 16 fsub 17 faddb 18 fadd 19 agnd 20 avcc 21 dpdd 22 dpdc 23 dpdb 24 dpda 25 datan 26 datap 27 tsubb 28 tsub 29 capan 30 capap 31 taddb 32 tadd 33 calreq 34 senb 35 sdata 36 sclk SM9103M npc
SM9103M nippon precision circuits? package dimensions (unit: mm) block diagram 2.44 to 2.64 0.85 15.20 to 15.40 7.40 to 7.60 0.29 to 0.39 0.80 0.10 to 0.30 0.51 to 1.01 10.11 to 10.51 0.63 0.10 7 0 to 8 0.23 to 0.32 7 0.51 0.20 45 r0.63 to 0.89 a b c d a+b+c+d (a+b)-(c+d) datap datan taddb tadd capap capan tsubb tsub dpda dpdb dpdc dpdd calreq fsub fsubb faddb fadd f2 f1 agnd avcc tempo tempi t4 t3 t2 t1 write mode sdata senb sclk vref to each block serial interface gain switching amplifier (ram read/write, rom read) analog signal processor offset canceller thermal sensor canceller control offset canceller gain switching amplifier differential output buffer amplifier gain switch (2db step) buffer buffer buffer buffer differential output buffer gain switch (2db step) amplifier analog signal processor +5v +5v dgnd dvcc
SM9103M nippon precision circuits? pin description number name i/o 1 1. i = input, ipd = input with built-in pull-down resistor, i/o = input/output, o = output function 1 mode ipd mode s witching/offset correction control input 1 2 write ipd mode s witching/offset correction control input 2 3 dgnd logic circuit g round. connect to the analog ground if there is no dedicated pickup or logic ground. 4 dvcc logic circuit supply. connect to the analog supply if there is no dedicated pickup or logic supply. 5 tempo o ther mal sensor test output. leave open for normal operation 6 tempi i ther mal sensor test input. leave open for normal operation 7 t1 i tracking pd input a 8 t2 i tracking pd input b 9 t3 i tracking pd input c 10 t4 i tracking pd input d 11 f1 i focus pd input e 12 f2 i focus pd input f 13 agnd analog circuit g round 14 vref i 2.0 v ref erence voltage input 15 fsubb i f ocus error signal f eedback input 16 fsub o f ocus error signal output 17 faddb i f ocus sum signal f eedback input 18 fadd o focus sum signal output 19 agnd analog circuit g round 20 avcc analog circuit supply 21 dpdd o buffered tracking signal output d for dpd servo 22 dpdc o buffered tracking signal output c for dpd servo 23 dpdb o buffered tracking signal output b for dpd servo 24 dpda o buffered tracking signal output a for dpd servo 25 datan o phase-modulated data signal diff erential inverting output 26 datap o phase-modulated data signal differential non-inverting output 27 tsubb i trac king push-pull signal f eedback input 28 tsub o trac king push-pull signal output 29 capan o id data signal differential inverting output 30 capap o id data signal differential non-inverting output 31 taddb i trac king pd sum signal f eedback input 32 tadd o tracking pd sum signal output 33 calreq o offset correction status/request output 34 senb i ser ial interf ace enable input 35 sdata i/o serial interf ace data input/acknowledge output 36 sclk i ser ial interf ace clock input
SM9103M nippon precision circuits? specifications absolute maximum ratings gnd = 0 v recommended operating conditions gnd = 0 v parameter symbol condition rating unit supply v oltage r ange v cc - 0.5 to 7.0 v input voltage r ange v in - 0.5 to v cc + 0.5 v input current r ange i in - 3.0 to +3.0 ma oper ating temperature r ange t opr 0 to 70 c storage temper ature r ange t stg - 40 to 125 c power dissipation p d 250 mw soldering temperature t sld 260 c soldering time t sld 10 s parameter symbol condition rating unit specs-guaranteed supply v oltage range v cc 4.75 to 5.25 v oper ating supply voltage r ange v cc 4.5 to 5.5 v reference voltage input v ref 1.89 to 2.11 v oper ating temperature r ange t opr 0 to 70 c
SM9103M nippon precision circuits? dc electrical characteristics v cc = 5 v ?5%, gnd = 0 v, t a = 0 to 70 c tracking pd input characteristics (t1, t2, t3, t4) v cc = 5 v ?5%, gnd = 0 v, t a = 0 to 70 c parameter symbol condition rating unit min typ max current consumption 1 1. 18 k w resistor connected between tsub and tsubb 47 k w resistor connected between t add and t addb 22 k w resistor connected betw een fsub and fsubb 27 k w resistor connected betw een fadd and f addb senb, sdata, sclk connected to gnd; all other pins (excluding supply and ground pins) open circuit. i cc1 oper ating mode 24 30 ma i cc2 sleep mode 1 mode, write, senb, sdata, sclk high-level input voltage v ih 0.8v cc v mode, write, senb, sdata, sclk low-level input voltage v il 0.2v cc v mode, write high-level input current i ih1 v in = v cc 50 100 200 a senb, sdata, sclk high-level input current i ih2 v in = v cc 3a mode, write, senb, sdata, sclk low-level input current i il v in = 0 v - 3 a calreq high-level output voltage v oh i oh = - 0.2 ma v cc - 0.2 v calreq low-level output voltage v ol1 i ol = 0.8 ma 0.4 v sdata low-level output voltage v ol2 i ol = 7 ma 1.0 v vref input current i ref v ref = 2.0 v 250 a parameter condition rating unit min typ max input impedance no signal 250 w input conversion noise current 100 khz to 10 mhz ram read 1 1. datap - datan output difference operation when 10 pf capacitors are connected to t1, t2, t3, t4 0.035 ? rms rom read 1 0.27 pin voltage no signal 1.5 v
SM9103M nippon precision circuits? data signal processor characteristics v cc = 5 v ?5%, gnd = 0 v, t a = 0 to 70 c parameter condition rating unit min typ max datap - datan current-to-voltage converter coef?ient 1 1. [datap - datan] = k [i t1 + i t2 + i t3 + i t4 ] ram read 10.0 12.5 15.0 k w rom read 2.50 3.12 3.74 capap - capan current-to-voltage converter coef?ient 2 2. [capap - capan] = k {[i t1 + i t2 ] - [i t3 + i t4 ]} ram read 11.3 14.1 16.9 k w datap, datan, capap, capan output impedance 100 w datap, datan, capap, capan output center voltage 3 3. 5 k w load connected to ground to prevent abnormal operation no signal 0.9v ref 1.1v ref v capap, capan output center voltage diff erence 3 no signal 50 mv datap, datan, capap, capan output oper ating output voltage 10 k w load, output center voltage ref erence - 0.7 +0.7 v variable coef?ient switching time ram ? rom read 10 ms saturation output reset time 4 4. converging to within ?al v alue ?10% ram wr ite ? ram read 500 ns datap, datan signal bandwidth 5 5. 10 pf input load capacitors connected to t1, t2, t3, t4. datap, dat an, capap, capan output load conditions shown below. f = 100 khz - 3 db frequency 19 mhz capap, capan signal bandwidth 5 f = 100 khz - 3 db frequency 20 mhz datap - datan, capap - capan gain peaking 5 f = 100 khz - 3 db frequency - 3 +0.5 db datap - datan, capap - capan group delay time 5 f = 1 to 10 mhz ?.0 ns 0.01 m f 0.01 m f 5pf 5pf 5pf 5pf 10k w datap datan 0.01 m f 0.01 m f 10pf 5pf 10pf 5pf 10k w capap capan
SM9103M nippon precision circuits? tracking signal processor characteristics v cc = 5 v ?5%, gnd = 0 v, t a = 0 to 70 c parameter condition rating unit min typ max tsub current-to-voltage conver ter coef?ient 1 ram read r f = 18 k w , v out = v ref 0.8 v 10.64 11.95 13.26 k w rom read 2.67 2.99 9.92 ram write 1.78 1.99 2.20 tadd current-to-voltage conver ter coef?ient 2 ram read r f = 47 k w 27.82 31.25 34.68 k w rom read 6.95 7.80 8.65 ram write 4.63 5.20 5.77 dpda, dpdb, dpdc, dpdd current-to-voltage converter coef?ient 3 ram read 40.0 50.0 60.0 k w rom read 10.0 12.5 15.0 t1, t2, t3, t4 converter coef?ient relative error tsub output, ram/rom read 2 % tsub, tadd, dpda, dpdb, dpdc, dpdd output impedance 100 w tsub oper ating output voltage 10 k w load connected to vref 1 3 v tadd, dpda, dpdb, dpdc, dpdd oper ating output voltage 10 k w load connected to vref v ref ?v converter coef?ient switching time ram read ? rom read 10 ms ram wr ite ? ram read 3 s tsub, t add signal bandwidth 4 dc to - 3 db frequency 1 mhz dpda, dpdb, dpdc, dpdd signal bandwidth 4 f = 100 khz to - 3 db frequency 5 mhz tsub, t add gain peaking 4 f = 10 khz to - 3 db frequency - 3 +0.5 db dpda, dpdb, dpdc, dpdd gain peaking 4 f = 100 khz to - 3 db frequency - 3 +4.0 db tsub phase response 4 @ f = 100 khz 10 dpda, dpdb, dpdc, dpdd g roup delay 4 f = 1 to 5 mhz group delay differential absolute value 5 ns relative error between 4 pins 1.0 tsub offset voltage no input signal, v ref reference, post-correction, t a = 25 c, r f = 18 k w ram read/wr ite max gain ?0.0 mv ram read, min to max gain ?6 ram read/wr ite diff erential gain max. 4 rom read, gain min/max ?00 tadd offset voltage no input signal, v ref reference ram read 30 mv rom read ?00 dpda, dpdb, dpdc, dpdd offset voltage no input signal, v ref reference ram/rom read - 550 +50 mv tsub offset voltage temperature coef?ient r f = 18 k w ?.4 mv/ c tsub variable gain r ange - 16 +14 db tsub variable gain step width 2 db
SM9103M nippon precision circuits? focus pd input characteristics (f1, f2) v cc = 5 v ?5%, gnd = 0 v, t a = 0 to 70 c focus signal processor characteristics v cc = 5 v ?5%, gnd = 0 v, t a = 0 to 70 c tsub gain s witching absolute accuracy v out = v ref ? 0.8 v - 16 to +8 db ?.5 db +10 to +14 db ?.0 1. tsub = k {[i t1 + i t2 ] - [i t3 + i t4 ]}, gain = 0 db 2. tadd = k [i t1 + i t2 + i t3 + i t4 ] 3. dpda = k i t1 , dpdb = k i t2 , dpdc = k i t3 , dpdd = k i t4 4. t1, t2, t3, t4: 10 pf input load capacitance tsub, tadd, dpda, dpdb, dpdc, dpdd: 10 pf output load capacitance tsub, t add: 10 k w load resistance dpda, dpdb, dpdc, dpdd: 100 k w load resistance parameter condition rating unit min typ max input impedance no signal 250 w input conversion noise current dc to 10 khz ram read 1 1. conversion from fsub output noise value when 14 pf capacitors connected to f1 and f2 24 na rms rom read 1 96 ram write 1 150 pin voltage no signal, v ref reference ?0 mv parameter condition rating unit min typ max fsub current-to-voltage conver ter coef?ient 1 ram read r f = 22 k w , v out = v ref 0.35 v 370 415 460 k w rom read 94 105 116 ram write 58 65 72 fadd current-to-voltage conver ter coef?ient 2 ram read r f = 27 k w 223 250 277 k w rom read 56.1 63 69.9 ram write 35.6 40 44.1 f1, f2 converter coef cient relative error fsub output, ram/rom read 2 % fsub, f add output impedance 100 w fsub oper ating output voltage 10 k w load connected to vref 1 3 v fadd oper ating output voltage 10 k w load connected to vref v ref ?v converter coef?ient switching time ram read ? rom read 10 ms ram wr ite ? ram read 3 s fsub, f add signal bandwidth 3 dc to - 3 db frequency 200 khz fsub, f add gain peaking 3 f = 10 khz to - 3 db frequency - 3 +0.5 db fsub, f add phase response 3 @ f = 10 khz 5 parameter condition rating unit min typ max
SM9103M nippon precision circuits? mode control logic offset correction characteristics v cc = 5 v ?5%, gnd = 0 v, t a = 0 to 70 c fsub offset voltage no input signal, v ref reference, post-correction, t a = 25 c ram read/write, rom read max gain ?.0 mv ram read, min to max gain ?1 ram read/wr ite diff erential gain max. 4 fadd offset voltage no input signal, v ref reference ?0 mv fsub offset voltage temperature coef?ient ?.22 mv/ c fsub variable gain r ange - 16 +14 db fsub variable gain step width 2 db fsub gain s witching absolute accuracy v out = v ref ? 0.35 v - 16 to +8 db ?.5 db +10 to +14 db ?.0 1. fsub = k [i f1 - i f2 ], gain = 0 db 2. fadd = k [i f1 + i f2 ] 3. f1, f2: 14 pf input load capacitance fsub, f add: 10 pf output load capacitance, 10 k w load resistance cont rol input operating mode offset correction write mode low or open low or open ram read active low or open high rom read high low or open ram write high high inactive parameter symbol condition rating unit min typ max tsub offset residual v ref reference, t a = 25 c ?.5 mv fsub offset residual v ref reference, t a = 25 c ?.5 mv supply voltage droop detect level v 1 1.9 2.8 3.7 v correction circuit startup supply voltage v 2 3.2 3.8 4.4 v v 1 and v 2 diff erence v 2 - v 1 0.7 1.0 1.3 v correction thermal sensor detect temper ature 15 20 25 c offset correction time 150 ms parameter condition rating unit min typ max
SM9103M nippon precision circuits?0 serial interface characteristics v cc = 5 v ?5%, gnd = 0 v, t a = 0 to 70 c parameter symbol condition rating unit min typ max sclk pulse cycle t cysck 100 ns sclk high-level pulsewidth t whsck 40 ns sclk low-level pulsewidth t wlsck 40 ns senb setup time t ssen 20 ns senb hold time t hsen 40 ns sdata setup time t ssda 15 ns sdata hold time t hsda 15 ns ack setup time 1 t sack 020ns ack hold time 1 t hack 50ns senb interval t insen 100 ns 1. ack is the acknowledge output (n-channel open-dr ain). low-level output when the data received is v alid. sdata load capacitance is 15 pf. senb sclock sdata controller sdata port tssen twhsck twlsck tcysck tssda thsda tsack thack tinsen thsen bit 0 bit 1 bit 15 lsb msb ack high impedance
SM9103M nippon precision circuits?1 functional description serial interface the SM9103M uses a serial interface comprising 2 ports to control and set tsub/fsub output gain switching, sleep mode to reduce current consump- tion, and tsub/fsub offset correction. the address and bit con?uration of each port is shown in table 1. serial data is input on sdata with the lsb ?st in sync with the falling edge of the sclk clock. after the 16th sclk falling edge and 16 bits of valid data has been input, the sdata n-channel open-drain output goes low to perform the function of an acknowledge signal. if the number of sclk cycles which occur when senb (serial interface enable) is high is less than 16, the received data is ignored and the internal port is not updated. if the number of sclk cycles is greater than 16, the data is still considered value up to the 16th sclk falling edge, the data is latched into the internal port, and the acknowledge signal is output. the acknowledge signal is held until senb goes low again. data signal processor this stage creates the data signal and id signal for output. the weak current from the tracking pd cells (t1, t2, t3, t4) are input to the front-end ampli?r where the signals are current-to-voltage converted at ?ed gain. the gain setting is controlled by pins write and mode. write switches between read/write, and mode switches the gain between values corre- sponding to high-re?ctivity and low-re?ctivity discs. these signals control the settings for ram (low-re?ctivity disc) read/write and rom (high-re?ctivity disc) read. the front-end ampli?r outputs are processed by the signal processor block to generate intermediate sig- nals. the data signal, (a + b + c + d), is converted to a difference signal by a differential output buffer and output on datap and datan. the id signal, generated from the difference between 2 signals, (a + b) and (c + d), is converted to a difference signal by a differential output buffer and output on capap and capan. the data signal (datap, datan) and id signal (capap, capan) dc components are removed using output stage capacitive networks. t1, t2, t3 and t4 have a hold function to provide the appropriate reverse bias required by the tracking pd to ensure the data read bandwidth. table 1. port address and bit con?uration 1 bit n umber 1514131211109876543210 data address msb lsb tg3 tg2 tg1 tg0 fg3 fg2 fg1 fg0 low low low low low sl1cs1 low low low low high 1. = don? care, ?= unassigned tg3 to tg0: tsub gain set bits. default = 0111 (0 db) fg3 to fg0: fsub gain set bits. def ault = 0111 (0 db) sl1: sleep mode set bit. sleep mode when 1, normal operation when 0. def ault = 0. cs1: offset correction control. offset correction when 1, nor mal operation when 0. def ault = 0.
SM9103M nippon precision circuits?2 tracking signal processor the tracking stage generates the push-pull tracking error signal and output signal for dpd servo, as well as a push-pull sum signal used as an auxiliary signal. the [(a + b) - (c + d)] signal from the com- mon-data front-end ampli?r and signal processor block is sent to the gain switching block. the gain switching block ampli?s the difference signal using one of 16 preset gain settings in 2 db steps to form a push-pull signal output on tsub. a feedback resis- tor connected to tsubb is used to ensure gain set- ting stability. the gain of the gain switching block is controlled by serial interface control bits as shown in table 2. each signal from t1, t2, t3, t4 is buffered and then output on dpda, dpdb, dpdc, dpdd, respec- tively, for dpd servos. the auxiliary signal is generated from the push-pull sum signal (a + b + c + d). this signal is buffered (tab) and output on tadd. a feedback resistor connected to taddb is used to ensure gain setting stability. focus signal processor the focus stage generates the focus error signal from the focus pd, and a sum signal. the weak focus pd current signals (f1, f2) are input to the front-end ampli?r and then current-to-voltage converted at ?ed gain. the front-end ampli?r output is sent to the signal processor block where the focus error signal (f1 - f2) and the sum signal (f1 + f2) are generated. the focus error signal is sent to the gain switching block. the gain switching block ampli?s the differ- ence signal using one of 16 preset gain settings in 2 db steps with output on fsub. a feedback resistor connected to fsubb is used to ensure gain setting stability. the gain of the gain switching block is con- trolled by serial interface control bits as shown in table 3. the sum is buffered and output on fadd. a feed- back resistor connected to faddb is used to ensure gain setting stability. table 2. tsub gain setting tg3 tg2 tg1 tg0 gain (db) 1 0000 +14 0001 +12 0010 +10 0011 +8 0100 +6 0101 +4 0110 +2 0111 0 1000 - 2 1001 - 4 1010 - 6 1011 - 8 1100 - 10 1101 - 12 1110 - 14 1111 - 16 1. default is 0 db table 3. fsub gain setting fg3 fg2 fg1 fg0 gain (db) 1 0000 +14 0001 +12 0010 +10 0011 +8 0100 +6 0101 +4 0110 +2 0111 0 1000 - 2 1001 - 4 1010 - 6 1011 - 8 1100 - 10 1101 - 12 1110 - 14 1111 - 16 1. default is 0 db
SM9103M nippon precision circuits?3 offset correction the SM9103M has built-in offset correction circuits for tracking and focus. during offset correction, the internal the device operates in ram read mode, and fsub and tsub operate at maximum gain (+14 db). the outputs on fsub, fadd and tsub are indeterminate. also, inputs t1, t2, t3, t4 and f1, f2 may be ignored. after correction is complete, the fsub and tsub gain settings return to their default values (0 db). offset correction is performed under the following conditions: n when power is applied. n when the supply drops below 2.8 ?0.9 v and then rises to above 3.8 ?0.6 v. n when sleep mode operation is cancelled. n when the serial interface bit cs1 is 1. note that if sl1 is also 1, then sl1 has priority. if the voltage falls below 2.8 ?0.9 v during offset correction, then correction stops and does not restart until the supply recovers to above 3.8 ?0.6 v. during offset correction, the calreq output is held high. calreq goes low after correction stops. the SM9103M also incorporates a temperature detect function which detects temperature changes of 20 ?5 c from the time the initial correction is per- formed. if a temperature change is detected, cal- req goes high and the device waits for an offset correction instruction. note that when both write and mode are high, offset correction is inactive and the output appears uncorrected. however, if a correction start condition occurs when correction is inactive, such as the cor- rection ?g cs1 set to 1, then correction operation is initiated internally but does not appear at the output unless correction is activated prior to correction operation ?ishing. once correction has been made inactive, the output remains uncorrected even if correction is subse- quently reactivated. in this case, the output remains uncorrected until a valid correction start condition is detected. sleep mode the SM9103M features a sleep mode which can be used when the device is not operating to signi?antly reduce current consumption. the sleep mode is con- trolled by serial interface bit sl1. preset function when power is applied or after offset correction, all serial interface ?gs are reset to their default values. flags tg3 to tg0 and fg3 to fg0 are also set to their default values in sleep mode. table 4. offset correction setting cs1 offset correction 1 1. default is no correction 0 no correction 1 correction table 5. sleep mode settings sl1 sleep mode 1 mode description low off normal operation high on sleep condition 1. default is off
SM9103M nippon precision circuits?4 nippon precision circuits inc. reserves the right to make changes to the products described in this data sheet in order to improve the design or performance and to supply the best possible products. nippon precision circuits inc. assumes no responsib ility for the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits are free from patent infringement. applications for any devices shown in this data sheet are for illustration only and nippon p recision circuits inc. makes no claim or warranty that such applications will be suitable for the use speci?d without further testing o r modi?ation. the products described in this data sheet are not intended to use for the apparatus which in?ence human lives due to the failu re or malfunction of the products. customers are requested to comply with applicable laws and regulations in effect now and hereinaft er, including compliance with export controls on the distribution or dissemination of the products. customers shall not export, dir ectly or indirectly, any products without ?st obtaining required licenses and approvals from appropriate government agencies. nippon precision circuits inc. 4-3, fukuzumi 2-chome koto-ku, tokyo 135-8430, japan telephone: 03-3642-6661 facsimile: 03-3642-6698 nc9806ae 1998.12 nippon precision circuits inc.

▲Up To Search▲

Price & Availability of SM9103M

	To Download SM9103M Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .